The present application relates to a semiconductor structure, a semiconductor device including said semiconductor structure and methods of fabricating the same. More particularly, the present application relates to a semiconductor structure including a nanoribbon-containing layer of alternating graphene nanoribbons separated by alternating insulating ribbons located atop a substrate and a method of fabricating such a structure. The present application also relates to a semiconductor device, such as a field effect transistor, that includes the semiconductor structure described above.
Several trends presently exist in the semiconductor and electronics industry including, for example, devices are being fabricated that are smaller, faster and require less power than the previous generations of devices. One reason for these trends is that personal devices such as, for example, cellular phones and personal computing devices, are being fabricated that are smaller and more portable. In addition to being smaller and more portable, personal devices also require increased memory, more computational power and speed. In view of these ongoing trends, there is an increased demand in the industry for smaller and faster transistors used to provide the core functionality of the integrated circuits used in these devices.
Accordingly, in the semiconductor industry there is a continuing trend toward fabricating integrated circuits (ICs) with higher densities. To achieve higher densities, there has been, and continues to be, efforts toward down scaling the dimensions of the devices on semiconductor wafers generally produced from bulk silicon. These trends are pushing the current technology to its limits. In order to accomplish these trends, high densities, smaller feature sizes, smaller separations between features, and more precise feature shapes are required in integrated circuits (ICs).
Significant resources go into down scaling the dimensions of devices and increasing packing densities. For example, significant time may be required to design such down scaled transistors. Moreover, the equipment necessary to produce such devices may be expensive and/or processes related to producing such devices may have to be tightly controlled and/or be operated under specific conditions. Accordingly, there are significant costs associated with exercising quality control over semiconductor fabrication.
In view of the above, the semiconductor industry is pursuing graphene to achieve some of the aforementioned goals. Graphene, which is essentially a flat sheet of carbon atoms, is a promising material for radio frequency (RF) transistors and other electronic transistors. Typical RF transistors are made from silicon or more expensive semiconductors such as, for example, indium phosphide (InP). The measured mobility of electrons in graphene was found to be as high as 200,000 cm2V−1s−1, while it is only about 5400 cm2V−1s−1 for InP and about 1400 cm2V−1s−1 for silicon.
With all its excellent electronic properties, graphene is missing a bandgap, making it unsuitable for fabrication of digital devices. Transistors fabricated using graphene in the channel would have Ion/Ioff ratios of the order of 10 or less, with many more orders of magnitude still required for proper function of such devices. It has been shown that bandgaps can be created in graphene if fabricated in the form of nanoribbons. The size of the bandgap increases with decreasing width of the nanoribbon and for potential practical application the width of the graphene nanoribbons (GNR) has to be less than 10 nm, preferably less than 5 nm.
Fabrication of GNR has been demonstrated before on exfoliated graphene nanoflakes. The prior art for fabrication of GNR is based on patterning and etching, usually by RIE, of the graphene layer. Such techniques form nanoribbons with non-uniform and potentially damaged edges, forming line edge roughness, LER, which deteriorates the electrical quality of the GNR.